Introduction

This table shows which BSA/SBSA rules are required for each level of those specifications.

How to use

There are few features you can use:

Some notes

Author info

Table is maintained by Marcin Juszkiewicz — AArch64/Arm developer working at Red Hat as Linaro assignee.

How to help

Sources used to generate table are available in git repository at github. Patches are always welcomed.

Section Rule ID BSA SBSA level 3 SBSA level 4 SBSA level 5 SBSA level 6 SBSA level 7
CPU architecture v8.0 v8.2 v8.4 v8.5 v8.6
SMMU v2 or v3 v3.0 v3.2 v3.2 v3.2
GIC v3.0 v3.0 v3.0 v3.0 v3.0
PE
Operating System
  B_PE_01 + + + + + +
  B_PE_02 + + + + + +
  B_PE_03 + + + + + +
  B_PE_04 + + + + + +
  B_PE_05 + + + + + +
  B_PE_06 + + + + + +
  B_PE_07 + + + + + +
  B_PE_08 + + + + + +
  B_PE_09 + + + + + +
  B_PE_10 + + + + + +
  B_PE_11 + + + + + +
  B_PE_12 + + + + + +
  B_PE_13 + + + + + +
  B_PE_14 + + + + + +
  B_PE_15 +
  B_PE_16 + + +
  B_PE_17 + + +
  B_SEC_01 + + +
  B_SEC_02 + + +
  B_SEC_03 + + +
  B_SEC_04 + + +
  B_SEC_05 + + +
  S_L3PE_01 + + + + +
  S_L3PE_02 + + + + +
  S_L3PE_03 + + + + +
  S_L3PE_04 + + + + +
  S_L4PE_01 + + + +
  S_L4PE_02 + + + +
  S_L4PE_03 + + + +
  S_L4PE_04 + + + +
  S_L5PE_01 + + +
  S_L5PE_02 + + +
  S_L5PE_03 + + +
  S_L5PE_04 + + +
  S_L5PE_05 + + +
  S_L5PE_06 + + +
  S_L5PE_07 + + +
  S_L6PE_01 + +
  S_L6PE_02 + +
  S_L6PE_03 + +
  S_L6PE_04 + +
  S_L6PE_05 + +
  S_L6PE_06 + +
  S_L7PE_01 +
  S_L7PE_02 +
  S_L7PE_03 +
  S_L7PE_04 +
  S_L7PE_05 +
  S_L7PE_06 +
  S_L7PE_07 +
  S_L7PE_08 +
  S_L7PE_09 +
  S_L7PE_10 +
  S_MPAM_PE + + +
  S_RAS_01 + +
  S_L7RAS_01 +
  S_L7RAS_02 +
  S_L7MP_01 +
  S_L7MP_02 +
  S_L7MP_03 +
  S_L7MP_04 +
  S_L7MP_05 +
  S_L7MP_06 +
  S_L7MP_07 +
  S_L7MP_08 +
Entropy
  S_L7ENT_01 +
Hypervisor
  B_PE_18 + + + + + +
  B_PE_19 + + + + + +
  B_PE_20 + + + + + +
  B_PE_21 + + + + + +
  B_PE_22 + + + + + +
Platform security
  B_PE_23 + + + + + +
  B_PE_24 + + + + + +
Memory map
Operating system
  B_MEM_01 + + + + + +
  B_MEM_02 + + + + + +
  B_MEM_03 + + + + + +
  B_MEM_04 + + + + + +
  B_MEM_05 + + + + + +
  B_MEM_06 + + + + + +
  B_MEM_07 + + + + + +
  B_MEM_07 + + + + + +
  S_L3MM_01 + + + + +
  S_L3MM_02 + + + + +
Platform security
  B_MEM_08 + + + + + +
  B_MEM_09 + + + + + +
Interrupts
Operating system
  B_GIC_01 +
  B_GIC_02 +
  B_GIC_03 + + + + + +
  B_GIC_04 + + + + + +
  B_GIC_05 + + + + + +
  S_L3GI_01 + + + + +
  S_L3GI_02 + + + + +
  S_L3PP_01 + + + + +
  S_L5GI_01 + + +
  S_L5GI_02 + + +
  B_PPI_01 + + + + + +
  S_L5PP_01 + + +
Hypervisor
  B_PPI_02 + + + + + +
Platform security
  B_PPI_03 + + + + + +
SMMU
Operating system
  B_SMMU_01 + + + + + +
  B_SMMU_02 + + + + + +
  B_SMMU_03 + + +
  B_SMMU_04 + + +
  B_SMMU_05 + + +
  B_SMMU_06 + + + + + +
  B_SMMU_07 + + + + + +
  B_SMMU_08 + + - - - -
  B_SMMU_09 + + + +
  B_SMMU_11 + + + +
  B_SMMU_12 + + + + + +
  B_SMMU_13 + + +
  B_SMMU_14 + + +
  S_L3SM_01 + + + + +
  S_L4SM_01 + - - -
  S_L4SM_02 + + + +
  S_L4SM_03 + + + +
  S_L5SM_01 + + +
  S_L5SM_02 + + +
  S_L5SM_03 + + +
  S_L5SM_04 + + +
  S_L6SM_01 + +
  S_L6SM_02 + +
  S_L6SM_03 + +
  S_L7SM_01 +
  S_L7SM_02 +
  S_L7SM_03 +
  S_L7SM_04 +
Hypervisor
  B_SMMU_16 + + + + + +
  B_SMMU_17 + + + + + +
  B_SMMU_18 + + + + + +
  B_SMMU_19 + + + + + +
  B_SMMU_20 + + + +
  B_SMMU_21 + + + + + +
  B_SMMU_22 + + + +
  B_SMMU_23 + + +
Platform security
  B_SMMU_24 +
  B_SMMU_25 +
Timer subsystem
Operating system
  B_TIME_01 + + + + + +
  B_TIME_02 + + + + + +
  B_TIME_03 + + + + + +
  B_TIME_04 + + + + + +
  B_TIME_05 + + + + + +
  B_TIME_06 + + + + + +
  B_TIME_07 + + + + + +
  B_TIME_08 + + + + + +
  B_TIME_09 + + + + + +
  B_TIME_10 + + + + + +
  S_L5TI_01 + + +
Power and wakeup
  B_WAK_01 + + + + + +
  B_WAK_02 + + + + + +
  B_WAK_03 + + + + + +
  B_WAK_04 + + + + + +
  B_WAK_05 + + + + + +
  B_WAK_06 + + + + + +
  B_WAK_07 + + + + + +
  B_WAK_08 + + + + + +
  B_WAK_10 + + + + + +
  B_WAK_11 + + + + + +
Peripherals
Operating system
  B_PER_01 + + + + + +
  B_PER_02 + + + + + +
  B_PER_03 + + + + + +
  B_PER_04 + + + + + +
  B_PER_05 + + + + + +
  B_PER_06 + + + + + +
  B_PER_07 + + + + + +
  B_PER_08 + + + + + +
  B_PER_09 + + + + + +
  B_PER_10 + + + + + +
  B_PER_12 + + + + + +
Platform security
  B_PER_11 + + + + + +
PCIe
  S_L4PCI_01 + + + +
  S_L4PCI_02 + + + +
  B_REP_1 + +
  B_IEP_1 + +
  S_PCIe_01 +
  S_PCIe_02 +
  S_PCIe_03 +
  S_PCIe_04 +
  S_PCIe_05 +
  PCIE_ER_01 +
  PCIE_ER_02 +
  PCIE_ER_03 +
  PCIE_ER_04 +
  PCIE_ER_05 +
  PCIE_ER_06 +
Watchdog
  B_WD_01 + + + + +
  B_WD_02 + + + + +
  B_WD_03 + + + + +
  B_WD_04 + + + + +
  B_WD_05 + + + + +
  B_WD_06 + + + + +
  S_L6WD_01 + +